Efficient
10x larger models| 100x efficiency
First-class hardware support for dual-sparsity neural networks for low memory footprint and high efficiency.
Sparse Processing Unit (SPU)
We’ve built our first-generation hardware platform to achieve the efficiency of an ASIC, while retaining the flexibility of a general purpose accelerator.
The SPU is easy to program, easy to simulate, and easy to deploy, allowing engineers and product managers to get innovative, class-leading products to market quicker.
The SPU is easy to program, easy to simulate, and easy to deploy, allowing engineers and product managers to get innovative, class-leading products to market quicker.
SPU-001
Integrate into your system today
Co-Processor
WLCSP for circuit integration
Bare die for systems in package (SiP) integration
Specifications:
- 1 MB of on-chip SRAM (10 MB effective with sparsity)
- 22nm process
- Sub-mW for speech, audio, and 1-D data
- SPI interface
Hardware IP
For System on a Chip (SoC) integration
Specifications:
- 512 kB of on-chip SRAM per core (5 MB effective with sparsity)
- Sharable memory
- 22nm process | portable to any process node
- Fractional or multi-core configurations
- AXI interface
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AI-ADAM100
SPU + MCU for on-device voice cleanup and flexible commands in a single affordable package
Specifications:
- SPU-001 NPU and Cortex-M0+ MCU
- 64/32 kB MCU code flash memory | 8 kB MCU SRAM
- 1 MB of NPU SRAM (10 MB effective with sparsity)
- NPU: 22 nm process | MCU: 130 nm process
- Sub-mW for speech, audio, and 1-D data
Get Started Today
Evaluation Board (EVB)
PCB with SPU-001 WLCSP for integrating with external host systems
Specifications:
- Full access to SPU pins on PMOD header
- 16 Mb onboard SPI Flash
- 1.8-3.3V operation
- Headers for easy power measurement
Evaluation Kit 2 (EVK2)
EVB + Tympan open source hearing aid platform and Tympan connector board
Specifications:
- Host processor Cortex-M7 with FPU
- 2x onboard MEMS microphones
- 3.5mm audio jacks for input/output
- Micro SD card reader
