Run sparse networks for 100x gains in performance by skipping zero connections and activations. Deploy as a co-processor or tileable IP.
Develop compressed sparse models in frameworks like PyTorch and TensorFlow with optimization tools, and benchmark performance with a hardware simulator.
Sparsified, quantized, fine-tuned, and ready-to-deploy neural networks for applications like speech enhancement, anomaly detection, neural beamforming and more!
We’ve built our hardware platform to achieve the efficiency of an ASIC, while retaining the flexibility of a general purpose accelerator. The SPU is easy to program, easy to simulate, and easy to deploy, allowing engineers and product managers to get innovative, class-leading products to market quicker.
10x larger models
100x efficiency
First-class hardware support for dual-sparsity neural networks for low memory footprint and high efficiency.
A wider range of applications and scales
Tileable, all-digital core design with 512 kB per core. Can be ported to different process nodes.
Less time deploying, more time designing
Deploy as a co-processor or IP from PyTorch or TensorFlow. Iterate with the model performance simulator.
Unrestricted to build the impossible
CNNs, RNNs, Transformers, and custom models supported with fine-grain optimization tools.
We’ve built our software development platform to help companies of all sizes deploy optimal sparse AI models for tomorrow’s applications and form factors. FemtoStack contains advanced sparse model optimization tools, a custom compiler, and a fast model performance simulator. It’s everything you need to go from exploration to deployment.
Train models from scratch or fine-tune pre-trained ones
Optimize models with sparsity regularization and quantization aware training
Simulate energy, latency, throughput, and footprint of your model on the SPU
Compile and deploy to FPGA for verification, or ASIC/SoC for production
