About Us

We build chips and AI algorithms for AI inference in edge devices with best-in-class energy consumption, area, speed, and cost. Our systems are based on a distributed, near-memory-compute architecture and sparse mathematics acceleration. End consumer products incorporating our technology include hearables, smart home appliances, security and environment monitors, displays, and more. Our products are being integrated into the designs of leading consumer electronics and IC design companies. The primary advantages of our products are ultra-low power consumption, ultra-low latency, and complete user privacy. Large-scale applications include always-on speech enhancement, super resolution, speech-to-text, and more. Existing technology limits compelling edge AI. Our mission is to enable AI applications natively, on-device which would be otherwise impossible.

Role Description

You are an experienced physical design engineer who has implemented and signed off multiple successful products using Cadence or Synopsys tools. You have substantial experience with both block level and full chip planning and implementation. You have taped out products in a variety of process nodes, both planar and FinFET. You are ready to work in a team environment to overcome technical challenges and bring novel AI products to market. 


  • Design and develop software in C++ and Python, likely using MLIR and other open-source ML compiler infrastructure
  • Implement innovative compiler optimization passes
  • Optimize fragmentation of large ML workloads across a multi-core architecture
  • Develop codegen techniques to leverage novel sparse computing hardware features
  • Identify requirements, blueprint solutions, and schedule deliverables
  • Collaborate closely with ML and hardware teams on cross-disciplinary projects


The candidate must have

  • 5+ years experience in professional software development
  • Proficiency in both Python and C++, with expertise in at least one
  • Familiarity with machine learning frameworks such as PyTorch and Tensorflow
  • Experience developing compilers or related system software
  • Familiarity with compiler concepts such as optimization passes, SSA form, code generation
  • MS or PhD in Computer Science, Electrical Engineering or a related field with coursework in  computer systems, or equivalent practical experience
  • Excellent technical communication and collaboration skills

The ideal candidate will also have

  • Experience building compilers for novel hardware
  • Experience working with open-source compiler ecosystems such as MLIR, LLVM and TVM
  • Experience working with the internals of open source deep learning frameworks
  • Experience with parallel programming and related program optimizations
  • Experience building and maintaining CI/CD pipelines
  • Experience with cross-platform software development, targeting Windows and Linux systems

Our Benefits

  • Competitive compensation including salary and stock options
  • Platinum Medical plan, Dental, Vision, Health FSA, and AD&D benefits
  • 401K
  • Unlimited paid vacation policy
  • Flexible WFH policy within the role’s responsibilities.

Equal Opportunity Statement

Femtosense is an equal opportunity employer committed to a diverse workforce with an inclusive working environment for everyone to do their best work. We do not discriminate on the basis of race, ethnicity, religion, gender, gender identity, sexual orientation, age, marital status, veteran status, or disability status.

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